Semiconductor device, manufacturing method and transistor circuit

ABSTRACT

A transistor circuit includes a first high electron mobility transistor and a second high electron mobility transistor having a negative threshold voltage, wherein a source of the second high electron mobility transistor is coupled to a gate of the first high electron mobility transistor, and a gate of the second high electron mobility transistor is coupled to a source of the first high electron mobility transistor.

CROSS-REFERENCE TO RELATED APPLICATION

This application is a divisional of application Ser. No. 13/351,869,filed Jan. 17, 2012, which is based upon and claims the benefit ofpriority of the prior Japanese Patent Application No. 2011-60723, filedon Mar. 18, 2011, the entire contents of which are incorporated hereinby reference.

FIELD

The embodiments discussed herein are related to a semiconductor device,a method for manufacturing the semiconductor device, and a transistorcircuit.

BACKGROUND

A GaN-HEMT (high electron mobility transistor) is promising as a highpower switching device from high breakdown electric field intensity andhigh mobility of GaN. Here, a thin insulating layer is provided directlyunderneath the gate to drive the GaN-HEMT by a voltage of the order ofseveral volts generated by an IC (integrated circuit). If a high voltageis applied between the source and the drain, the thin insulating layeris easily broken. In other words, the withstand voltage of the GaN-HEMTitself is not high.

To cope therewith, a semiconductor device having a field plate (FP) onthe GaN-HEMT has been proposed (hereafter referred to as GaN-FP-HEMT).According to the GaN-FP-HEMT, the withstand voltage of the GaN-HEMTrelative to the source-drain voltage is increased to several hundredvolts. (For example, refer to Wataru Saito, “Field-Plate StructureDependence of Current Collapse Phenomena in Hight-Voltage GaN-HEMTs”,IEEE Electron device, Vol. 31, July, 2010, No. 7, pp. 559-661, July2010.)

SUMMARY

According to an aspect of the embodiment, a transistor circuit includesa first high electron mobility transistor and a second high electronmobility transistor having a negative threshold voltage, wherein asource of the second high electron mobility transistor is coupled to agate of the first high electron mobility transistor, and a gate of thesecond high electron mobility transistor is coupled to a source of thefirst high electron mobility transistor.

The object and advantages of the invention will be realized and attainedby means of the elements and combinations particularly pointed out inthe claims.

It is to be understood that both the foregoing general description andthe following detailed description are exemplary and explanatory and arenot restrictive of the invention, as claimed.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a circuit diagram of a transistor circuit according to theembodiment 1;

FIG. 2 is a cross section of the first high electron mobilitytransistor;

FIG. 3 is a cross section of the second high electron mobilitytransistor;

FIG. 4 is a diagram illustrating the operation of the transistor circuitaccording to the embodiment 1;

FIG. 5 is a circuit diagram illustrating a deformation example of theembodiment 1;

FIG. 6 is a plan view of a transistor circuit according to theembodiment 2;

FIG. 7 is a plan view of a deformation example of the embodiment 2;

FIG. 8 is a circuit diagram of a transistor circuit according to theembodiment 3;

FIG. 9 illustrates an exemplary cross-sectional view of the first highelectron mobility transistor;

FIG. 10 illustrates an exemplary cross-sectional view of the second highelectron mobility transistor;

FIG. 11A is a process cross section illustrating an exemplary method formanufacturing a transistor circuit according to the embodiment 3;

FIG. 11B is a process cross section illustrating an exemplary method formanufacturing a transistor circuit according to the embodiment 3;

FIG. 11C is a process cross section illustrating an exemplary method formanufacturing a transistor circuit according to the embodiment 3;

FIG. 12A is a process cross section illustrating an exemplary method formanufacturing a transistor circuit according to the embodiment 3;

FIG. 12B is a process cross section illustrating an exemplary method formanufacturing a transistor circuit according to the embodiment 3;

FIG. 12C is a process cross section illustrating an exemplary method formanufacturing a transistor circuit according to the embodiment 3;

FIG. 13A is a process cross section illustrating an exemplary method formanufacturing a transistor circuit according to the embodiment 3;

FIG. 13B is a process cross section illustrating an exemplary method formanufacturing a transistor circuit according to the embodiment 3;

FIG. 13C is a process cross section illustrating an exemplary method formanufacturing a transistor circuit according to the embodiment 3;

FIG. 14A is a process cross section illustrating an exemplary method formanufacturing a transistor circuit according to the embodiment 3;

FIG. 14B is a process cross section illustrating an exemplary method formanufacturing a transistor circuit according to the embodiment 3;

FIG. 15A is a process cross section illustrating an exemplary method formanufacturing a transistor circuit according to the embodiment 3; and

FIG. 15B is a process cross section illustrating an exemplary method formanufacturing a transistor circuit according to the embodiment 3.

EMBODIMENTS

As described previously, introducing the FP increases the withstandvoltage of the GaN-HEMT relative to the source-drain voltage. However,since the thickness of the insulating layer right underneath the gatedoes not change, the withstand voltage of the GaN-FP-HEMT relative tothe source-gate voltage is not high. Therefore, when a noise of theorder of several tens of volts is applied to the gate, the GaN-FP-HEMTis broken.

Now, an electrostatic noise easily reaches several hundred volts. Ifsuch a high voltage is applied between the source and the drain, theremay be cases that even the GaN-FP-HEMT, having an enhanced withstandvoltage relative to the source-drain voltage by the field plate, may bebroken.

As such, the high electron mobility transistor has an insufficientwithstand voltage for high voltage operation.

Embodiments will be explained with reference to accompanying drawings.

Embodiment 1 (1) Structure

FIG. 1 is a circuit diagram of a transistor circuit 2 according to thepresent embodiment. The transistor circuit 2 includes a first highelectron mobility transistor 4 and a second high electron mobilitytransistor 6 having a negative threshold voltage. In the frames of FIG.1 depicted with broken lines, the equivalent circuits of the first andthe second high electron mobility transistors 4, 6 are illustrated.

As illustrated in FIG. 1, the second source S2 of the second highelectron mobility transistor 6 is coupled to a first gate G1 of thefirst high electron mobility transistor 4. Also, the second gate G2 ofthe second high electron mobility transistor 6 is coupled to a firstsource 51 of the first high electron mobility transistor 4.

FIG. 2 is a cross section of the first high electron mobility transistor4. As illustrated in FIG. 2, the first high electron mobility transistor4 includes a semiconductor heterojunction 10 disposed on a substrate 8.The substrate 8 is, for example, a Si substrate.

As illustrated in FIG. 2, the semiconductor heterojunction 10 has aheterostructure including a channel layer 12 and a barrier layer 14stacked thereon. The channel layer 12 is an undoped GaN layer, forexample. The barrier layer 14 is either an undoped or an n-type AlGaNlayer, for example. Namely, the semiconductor heterojunction 10 is anAlGaN/GaN heterojunction, for example.

In the AlGaN/GaN heterojunction, piezo polarization is produced due tolattice distortion between the AlGaN barrier layer and the GaN channellayer. By the above piezo polarization and spontaneous polarization,two-dimensional electron gas is generated at the interface between theAlGaN barrier layer and the GaN.

As illustrated in FIG. 2, the first high electron mobility transistor 4includes a first source 51, a first gate G1, a first field plate FP1 anda first drain D1. The first FP1 is disposed between the first gate G1and the first drain D1, and is coupled to the first source 51 by awiring 15 (refer to FIG. 1).

As illustrated in FIG. 2, a first insulating film 24 such as a SiN filmis provided on the barrier layer 14. On a laminated film 26 in which thebarrier layer 14 and the first insulating film 24 are laminated, a firstgate recess 28 is provided to reach the inside of the barrier layer 14.

As illustrated in FIG. 2, the first gate G1 is provided in the firstgate recess 28. Further, a first gate insulating layer 30 is providedbetween the first gate G1 and the laminated film 26. The first gateinsulating layer 30 is, for example, a laminated film including AlN filmand SiN film.

Also, on the laminated film 26, an FP recess 28 a is provided to reachthe surface of the barrier layer 14. The field plate FP1 is provided inthe FP recess 28 a. Further, an FP insulating layer 30 a is providedbetween the FP recess 28 a and the laminated film 26. Similar to thegate insulating layer 30, the FP insulating layer 30 a is, for example,a laminated film including AlN film and SiN film. As illustrated in FIG.2, the above field plate FP1 extends between the first gate G1 and thefirst drain D1.

Further, on the laminated film 26, a source recess 29 a is provided toreach the inside of the barrier layer 14. A portion of the first sourceS1 is provided in the source recess 29 a. Also, on the laminated film26, a drain recess 29 b is provided to reach the inside of the barrierlayer 14. A portion of the first drain D1 is provided in the drainrecess.

On the first insulating film 24, a second insulating film 29 composed ofSiO₂ or the like is provided, in such a manner as to cover the firstsource S1, the first gate G1, the first field plate FP1 and the firstdrain D1. By a wiring 17 (refer to FIG. 1) provided on the secondinsulating film 29, the first field plate FP1 is coupled to the sourceS1.

FIG. 3 is a cross section of the second high electron mobilitytransistor 6. The structure of the second high electron mobilitytransistor 6 is substantially identical to the structure of the firsthigh electron mobility transistor 4, except for that it does not includethe first field plate FP1 and that the second gate recess 28 b virtuallyreaches the surface of the barrier layer 14 without penetrationtherefrom.

The structure of the second gate G2 of the second high electron mobilitytransistor 6 is substantially identical to the structure of the firstfield plate FP1 of the first high electron mobility transistor 4, asillustrated in FIG. 3. Namely, the second gate G2 is provided in thesecond gate recess 28 b which is provided on the laminated film 26 toreach the surface of the barrier layer 14. A second gate insulatinglayer 30 b is provided between the second gate recess 28 b and thelaminated film 26.

The first high electron mobility transistor 4 and the second highelectron mobility transistor 6 are simultaneously formed on theidentical substrate 8, for example. The first and the second gateinsulating layers 30, 30 b and the FP insulating layer 30 a are formedof a single insulating layer, as an example.

A second source S2 of the second high electron mobility transistor 6 iscoupled to the first source S1 of the first high electron mobilitytransistor 4, by means of a wiring 19 (refer to FIG. 1) provided on thesecond insulating film 29.

The gate G1 of the first HEMT 4 and the heterostructure 10 in thevicinity thereof (inclusive of the first gate insulating layer 30) has afunction of HEMT. Also, the first field plate FP1 and theheterostructure 10 in the vicinity thereof (inclusive of the FPinsulating layer 30 a) has a function of HEMT. Therefore, as illustratedin FIG. 1, the equivalent circuit of the first high electron mobilitytransistor 4 is a series circuit including a HEMT 32 corresponding tothe first gate G1 and a HEMT 34 corresponding to the first field plateFP1 (hereafter referred to as first FP-HEMT).

The threshold of the HEMT 32 corresponding to the first gate G1 is, forexample, 1 to 3 V. Also, the withstand voltage of the insulating layer30 underneath the first gate G1 relative to a voltage between the firstsource S1 and the first gate G1 (hereafter referred to as the withstandvoltage of the first gate) is, for example, in the order of 10 V.

The threshold of the first FP-HEMT 34 is a negative voltage of, forexample, −7 to −8 V. The absolute value of the threshold of the firstFP-HEMT 34 (for example, 7 to 8 V) is smaller than the withstand voltageof the first gate G1 (for example, in the order of 10 V). Hereafter, theabsolute value of the threshold is referred to as a threshold absolutevalue.

The barrier layer 14 underneath the first gate G1 is thinner than thebarrier layer 14 underneath the first FP1. Accordingly, the threshold ofthe HEMT 32 (1 to 3 V, for example) corresponding to the first gate G1is higher than the threshold of the first FP-HEMT (−7 to −8 V, forexample). On the other hand, the withstand voltage of the first gate G1(10 V, for example) is lower than the withstand voltage of the firstfield plate FP1 (100 V, for example).

Here, the withstand voltage of the first field plate FP1 is a withstandvoltage of the insulating layer 30 a underneath the first field plateFP1 (hereafter referred to as the withstand voltage of the first fieldplate FP1) relative to the source-gate voltage of the first FP-HEMT. Thesource-gate voltage of the first FP-HEMT is a voltage between a node N1,which is located between the first gate G1 and the first field plateFP1, and the first field plate FP1.

The second high electron mobility transistor 6 has a negative thresholdvoltage (for example, −7 to −8 V). Here, the threshold absolute value ofthe second high electron mobility transistor 6 is higher than thethreshold of the HEMT 32 (for example, in the order of 1 to 3 V)corresponding to the first gate G1. Also, the withstand voltage of thegate G2 of the second high electron mobility transistor 6 (for example,in the order of 100 V) is higher than the withstand voltage of the gateG1 of the first high electron mobility transistor 4 (for example, in theorder of 10 V).

Additionally, the structure underneath the second gate G2 of the secondhigh electron mobility transistor 6 according to the present embodimentis substantially identical to the structure underneath the first fieldplate FP1, as illustrated in FIG. 2. Therefore, the characteristics(threshold, withstand voltage, etc.) of the second high electronmobility transistor 6 are substantially identical to the characteristicsof the first FP-HEMT 34. However, the structure underneath the secondhigh electron mobility transistor 6 may be different from the structureunderneath the first field plate FP1.

Here, the withstand voltage of the gate is a withstand voltage (avoltage immediately before the occurrence of a dielectric breakdown) ofthe insulating layer underneath the gate, relative to the source-gatevoltage of the HEMT corresponding to the gate. The withstand voltage ofthe field plate is a withstand voltage (a voltage immediately before theoccurrence of a dielectric breakdown) of the insulating layer underneaththe field plate, relative to the source-gate voltage of the HEMTcorresponding to the field plate.

Hereafter, the withstand voltage of the gate and the withstand voltageof the field plate are comprehensively referred to as gate withstandvoltage. Also, the breakdown of the insulating layer underneath the gate(or the field plate) is expressed as gate (or field-plate) breakdown.

Incidentally, the HEMT has a symmetric structure with respect to thegate. Accordingly, the withstand voltage of the gate (or the fieldplate) relative to the drain-gate voltage is substantially identical tothe withstand voltage of the gate (or the field plate) relative to thesource-gate voltage.

(2) Operation

As illustrated in FIG. 1, the source S1 and the drain D1 of the firsthigh electron mobility transistor 4 are coupled to a source terminal STand a drain terminal DT of the transistor circuit 2, respectively. Thedrain D2 of the second high electron mobility transistor 6 is coupled toa gate terminal GT of the transistor circuit 2. A positive voltage (ofthe order of several tens of volts, for example) is applied to the drainterminal DT, and the ground potential (=0 V) is supplied to the sourceterminal ST.

FIG. 4 is a diagram illustrating the operation of the transistor circuit2 according to the present embodiment. The horizontal axis representstime. The vertical axis represents a voltage relative to the groundplane (i.e., potential). The solid lines indicate a potential 38 at thegate G1 of the first high electron mobility transistor 4. The brokenlines indicate a potential 36 applied to the gate terminal GT (hereafterreferred to as gate drive potential). The upper portion of FIG. 4illustrates four phases P1-P4 corresponding to the operating states ofthe second high electron mobility transistor 6.

Now, a source-gate potential of the second high electron mobilitytransistor 6 is a potential difference between a potential V_(S2) at thesecond source S2 and a potential V_(G2) at the second gate G2(=V_(G2)−V_(S2)). As illustrated in FIG. 1, the source S2 of the secondhigh electron mobility transistor 6 is coupled to the first gate G1.Therefore, the potential V_(S2) at the source S2 of the second highelectron mobility transistor 6 equals the potential V_(G1) at the firstgate G1 (V_(S2)=V_(G1)).

Also, the potential V_(G2) at the gate G2 of the second high electronmobility transistor 6 equals the potential V_(S1) at the first source(V_(G2)=V_(S1)). Here, the potential V_(S1) at the first source coupledto the source terminal ST is the ground potential (=0 V). Therefore, thepotential V_(G2) at the gate G2 of the second high electron mobilitytransistor 6 is 0 V (V_(G2)=0 V).

Accordingly, a source-gate potential V_(SG) (=V_(G2)−V_(S2)) of thesecond high electron mobility transistor 6 is represented by equation(1).

V _(SG) =−V _(G1)  (1)

——Phase P1——

Phase P1 is a period during which a drive potential applied to the gateterminal GT (hereafter referred to as gate drive potential) is kept in alow level. In the example illustrated in FIG. 4, the low level potential(potential level to cause the transistor circuit 2 to be in anon-conductive state) is 0 V. The potential V_(G1) of the first gate G1at this time is 0 V. Therefore, as is apparent from equation (1), thesource-gate potential V_(SG) of the second high electron mobilitytransistor 6 is 0 V.

As described earlier, the threshold of the second high electron mobilitytransistor 6 is a negative voltage (−7 to −8 V, for example). Therefore,the second high electron mobility transistor 6 is conductive because thesource-gate potential V_(SG) (=0 V) is not lower than the threshold(negative voltage).

——Phase P2——

Phase P2 is a period starting from the time the gate drive potential 36starts rising from the low level, and lasting until reaching thethreshold absolute value of the second high electron mobility transistor6. In the example illustrated in FIG. 4, the peak value of the gatedrive potential (for example, in the order of 14 to 16 V) isapproximately twice as large as the threshold of the first high electronmobility transistor 4 (for example, in the order of 7 to 8 V). Here, thepeak value is high level potential.

When the gate drive potential starts rising, a current is supplied tothe first gate G1 through the second high electron mobility transistor 6which is in a conductive state. By the above current, the source-gatecapacitance of the first high electron mobility transistor 4 is charged.As a result, the potential 38 at the first gate G1 rises together withthe gate drive potential 36.

——Phase P3——

Phase 3 is a period starting from when the gate drive potential 36further rises from the threshold absolute value of the second highelectron mobility transistor 6, and after descending, lasting untilreturning again to the threshold absolute value of the second highelectron mobility transistor 6.

When the gate drive potential 36 exceeds the threshold absolute value ofthe second high electron mobility transistor 6 (for example, 7 to 8 V),the potential V_(G1) at the first gate G1 reaches a potential whichslightly exceeds the threshold absolute value of the second highelectron mobility transistor 6. Then, as is apparent from equation (1),the source-gate potential V_(SG) of the second high electron mobilitytransistor 6 becomes slightly lower than the threshold of the secondhigh electron mobility transistor 6. At this time, the second highelectron mobility transistor 6 becomes a non-conductive state.

By this, charging the source-gate capacitance of the first high electronmobility transistor 4 is stopped. Accordingly, the potential V_(G1) atthe first gate G1 does not rise higher than the threshold absolute valueof the second high electron mobility transistor 6 or to that degree.

Thereafter, the gate drive potential 36 reaches a high level potential,and maintains the high level potential for a while. Then, the gate drivepotential 36 starts descending, and reaches again the threshold absolutevalue of the second high electron mobility transistor 6. During theabove period, the second high electron mobility transistor 6 remains inthe non-conductive state. Therefore, the potential V_(G1) at the firstgate G1 is maintained at the threshold absolute value of the second highelectron mobility transistor 6, or to that degree.

——Phase P4——

Phase P4 is a period after the gate drive potential 36 descends to thethreshold absolute value of the second high electron mobility transistor6 or lower.

A drain-gate voltage V_(DG) of the second high electron mobilitytransistor 6 is a potential difference between a potential V_(D2) of thesecond drain D2 and a potential V_(G2) of the second gate G2(=V_(G2)−V_(D2)). As described earlier, the potential V_(G2) at thesecond gate G2 is 0 V. Accordingly, the drain-gate voltage V_(DG) of thesecond high electron mobility transistor 6 is represented by equation(2).

V _(DG) =−V _(D2)  (2)

Therefore, when the gate drive potential 36 becomes lower than theabsolute threshold of the second high electron mobility transistor 6,the drain-gate potential of the second high electron mobility transistor6 becomes the threshold or higher. This causes the second high electronmobility transistor 6 to be conductive. Then, the source-gatecapacitance of the first high electron mobility transistor 4 isdischarged through the second high electron mobility transistor 6. As aresult, the potential 38 of the first gate G1 descends together with thegate drive potential 36.

The discharge of the source-gate capacitance of the first high electronmobility transistor 4 continues until the gate drive potential 36reaches the low level. When the gate drive potential 36 reaches the lowlevel, the discharge is stopped.

As a result, the potential 38 at the first gate G1 descends to the lowlevel potential (=0 V), and thereafter, is maintained at the low levelpotential. The states of the first and the second transistors 4, 6 afterthe gate drive potential 36 reaches the low level potential correspondto the states of the first and the second high electron mobilitytransistors 4, 6 at Phase P1.

——Conduction Control——

As described earlier by reference to FIG. 4, the potential 38 at thefirst gate G1 rises to the threshold absolute value of the second highelectron mobility transistor 6 or to that degree, together with the gatedrive potential 36. After remaining at approximately the thresholdabsolute value for a while, the potential 38 at the first gate G1descends along with the gate drive potential 36. As described earlier,the threshold absolute value of the second high electron mobilitytransistor 6 (for example, 7 to 8 V) is higher than the threshold of theHEMT 32 (for example, in the order of 1 to 3 V) corresponding to thefirst gate G1.

Therefore, when the gate drive potential 36 reaches the high levelpotential, the HEMT 32 corresponding to the first gate G1 becomesconductive. Then, a potential difference between the source of the firstFP-HEMT (i.e. the first node N1) and the first field plate FP1 becomes 0V, and thus, the first FP-HEMT becomes conductive. By this, the firsthigh electron mobility transistor 4 becomes conductive.

On the other hand, when the gate drive potential 36 reaches the lowlevel, the HEMT 32 corresponding to the first gate G1 becomesnon-conductive. Then, as will be described later, a potential differencebetween the source and the first field plate FP1 of the first FP-HEMT 34becomes the threshold of the FP-HEMT 34 or less, and thus, the firstFP-HEMT 34 becomes the non-conductive state. By this, the first highelectron mobility transistor 4 becomes the non-conductive state.

In such a manner, the conductive state of the first high electronmobility transistor 4 is controlled by the gate drive potential 36.

——Withstand Voltage——

As described above, the peak value of the first gate potential 38(V_(G1)) is as high as the absolute value ABS V_(th) of the threshold ofthe second high electron mobility transistor 6 or to that degree. Here,the absolute threshold value ABS V_(th) of the second high electronmobility transistor 6 (for example, 7 to 8 V) is lower than thewithstand voltage BV (for example, in the order of 10 V) of the firstgate G1 (the order of V^(G1)=ABS V_(th)<BV). Therefore, the first gatepotential V_(G1) is lower than the withstand voltage of the gate of thefirst high electron mobility transistor (V_(G1)<BV).

Here, the first gate potential 38 (V_(G1)) is a source-gate voltage ofthe first high electron mobility transistor 4. Therefore, according tothe present transistor circuit 2, the source-gate voltage (=V_(G1)) ofthe first high electron mobility transistor 4 is limited to a voltagelower than the gate withstand voltage BV of the first high electronmobility transistor 4, by the second high electron mobility transistor6. Accordingly, the first gate G1 is not broken by a potential appliedto the gate terminal GT. In other words, the first high electronmobility transistor 4 is protected by the second high electron mobilitytransistor 6.

For example, the first gate G1 may not be broken even if the high levelpotential of the gate drive potential is higher than, inclusive of, thewithstand voltage of the first high electron mobility transistor 4.Also, the first gate G1 may not be broken even when a voltage higherthan, inclusive of, the withstand voltage is applied to the gateterminal GT due to a noise.

Additionally, the withstand voltage of the second high electron mobilitytransistor 6 is, for example, in the order of 100 V. Therefore, thesecond high electron mobility transistor 6 may not be broken even when anoise of the order of tens of volts is applied to the gate terminal GT.

As such, in the semiconductor device 2 according to the presentembodiment, the second high electron mobility transistor 6 limits avoltage between the source and the gate of the first high electronmobility transistor 4 to a voltage smaller than the gate withstandvoltage of the first high electron mobility transistor 4. By this, thebreakage of the first high electron mobility transistor 4 is prevented.Here, the “a voltage between the source and the gate” means a valueequivalent to the absolute value of a voltage between the source and thegate.

In the above-mentioned description, a case that a positive potential isapplied to the gate terminal GT is assumed. In this case, the positivepotential is applied to the first gate G1, by which two-dimensionalelectron gas is generated in the channel layer 12 underneath the gate.By this, a large electric field is applied to the insulating layer 30and the barrier layer 14, which causes easy breakage of the insulatinglayer 30 and the barrier layer 14. According to the present embodiment,by providing the second high electron mobility transistor 6, theelectric field applied to the insulating layer 30 and the barrier layer14 is limited, so that the breakage of the insulating layer 30 and thebarrier layer 14 is prevented.

On the other hand, when a noise having a potential changed to benegative is input to the gate terminal GT, a negative potential is alsoapplied to the first gate G1. In this case, the two-dimensional electrongas is not generated, and a depletion layer is expanded in the channellayer 12. By this, the electric field applied to the insulating layer 30and the barrier layer 14 is hard to be strengthened. Therefore, thoughany special measure is taken, the transistor circuit 2 according to thepresent embodiment may not be easily broken if a noise having apotential changed to be negative is input to the gate terminal.

——Field Plate FP1——

As illustrated in FIG. 1, the first node N1 exists between the firstfield plate FP1 and the first gate G1. In a state that a high levelpotential is applied to the gate terminal GT, the HEMT 32 correspondingto the first gate G1 and the first FP-HEMT 34 are conductive. At thistime, a potential at the first node N1 is approximately 0 V.

When a low level potential is applied to the gate terminal GT, the HEMT32 corresponding to the first gate G1 becomes a non-conductive state.Then, a parasitic capacitance (not illustrated) parasitic on the firstnode N1 is charged via the first FP-HEMT 34.

By this charge, the potential at the first node N1 rises. When thepotential at the first node N1 slightly exceeds the threshold absolutevalue of the first FP-HEMT 34 (for example, in the order of 7 to 8 V),the source-gate voltage of the first FP-HEMT 34 becomes slightly lowerthan the threshold thereof. This makes the first FP-HEMT 34non-conductive, and also the parasitic capacitance not charged any more.As a result, the potential at the first node N1 becomes the thresholdabsolute value of the first FP-HEMT 34 or to that degree.

The threshold absolute value of the first FP-HEMT 34 (for example, inthe order of 7 to 8 V) according to the present embodiment is lower thanthe gate withstand voltage of the HEMT 32 (for example, in the order of10 V) corresponding to the first gate G1. Accordingly, the first highelectron mobility transistor 4 may not be broken even when a potential(of several tens volts, for example) higher than the withstand voltageof the HEMT 32 corresponding to the first gate G1 (relative to thesource-drain voltage) is applied to the drain terminal DT. In otherwords, the HEMT 32 corresponding to the first gate G1 is protected bythe first FP-HEMT 34.

Additionally, when the withstand voltage of the first high electronmobility transistor 4 is sufficiently high, or when a large voltage isnot applied to the drain terminal DT, the first FP-HEMT FP1 is notneeded.

Incidentally, when the high electron mobility transistor is in aconductive state, the drain potential is substantially 0 V. Therefore,the gate may not be broken. On the other hand, if the field plate is notprovided, the gate may easily be broken when the high electron mobilitytransistor becomes non-conductive. In that case, when the high electronmobility transistor becomes non-conductive, an increase of the drainpotential results in breakage of the gate.

In the above example, the threshold of the HEMT 32 corresponding to thefirst gate G1 is a positive voltage. However, the threshold of the HEMT32 corresponding to the first gate G1 may also be a negative voltage.

Also, in the above example, the ground potential is supplied to thesource terminal ST. However, either a positive potential or a negativepotential may be supplied to the source terminal ST. In that case, thetransistor circuit 2 is operated substantially in the same manner as inthe above description, only by substituting the potential supplied tothe source terminal ST, from the ground potential to the negativepotential or the positive potential. The gate withstand voltage of thetransistor circuit 2 also becomes higher, for the same reason asdescribed above.

(3) Deformation Example

FIG. 5 is a circuit diagram illustrating a deformation example 2a of thepresent embodiment. In the deformation example 2a, a third high electronmobility transistor 40 coupled in series with the second high electronmobility transistor 6 is provided, as illustrated in FIG. 5.

A third gate G3 of the third high electron mobility transistor 40 iscoupled to the first drain D1 of the first high electron mobilitytransistor 4. The threshold of the third high electron mobilitytransistor 40 is a negative voltage. Also, the threshold absolute valueof the third high electron mobility transistor 40 is higher than thethreshold of the first high electron mobility transistor 4, and is lowerthan the gate withstand voltage of the first high electron mobilitytransistor 4. Such characteristics are obtained by configuring the thirdhigh electron mobility transistor 40 with a structure substantiallyidentical to that of the second high electron mobility transistor 6.

In the aforementioned “(2) Operation”, as a premise, the potential atthe source terminal ST is lower than the potential at the drain terminalDT. However, the potential at the source terminal ST is not always lowerthan the potential at the drain terminal DT. For example, when a largenoise current flows in wiring which connects the ground plane to thesource terminal ST, there is a case that the potential at the sourceterminal ST is higher than the potential at the drain terminal DT.

In this case, the second high electron mobility transistor 6 does noteasily become a non-conductive state, because a high potential at thesource terminal ST is applied to the gate of the second high electronmobility transistor 6. Therefore, it is difficult for the second highelectron mobility transistor 6 to limit the potential rise of the firstgate G1, when a gate drive potential is applied to the gate terminal GT.

In contrast, the third high electron mobility transistor 40 includingthe gate G3 coupled to the drain terminal DT of a lower potential sideeasily becomes a non-conductive state. Therefore, if the gate drivepotential rises, the third high electron mobility transistor 40 becomesthe non-conductive state, and the potential rise of the first gate G1 islimited.

At this time, a potential difference between the first gate G1 and thefirst source 51, or the source-gate voltage, is limited to the thresholdabsolute value of the third high electron mobility transistor 40 or tothat degree. The above threshold absolute value is lower than thewithstand voltage of the first high electron mobility transistor 4.Therefore, according to the deformation example 2a, it is possible toprevent the breakage of the first gate G1, even if the potential at thesource terminal ST becomes higher than the potential at the drainterminal.

Further, the threshold absolute value of the third high electronmobility transistor 40 is higher than the threshold of the HEMT 32corresponding to the first gate G1. Therefore, the third high electronmobility transistor 40 does not prevent the conduction of the first highelectron mobility transistor 4. Here, the third high electron mobilitytransistor 40 may also be provided between the first gate G1 and thesecond high electron mobility transistor 6.

Embodiment 2

FIG. 6 is a plan view of a transistor circuit 2 b according to thepresent embodiment. In the embodiment 1, one first high electronmobility transistor 4 is coupled to one second high electron mobilitytransistor 6. On the other hand, in the transistor circuit 2 b accordingto the present embodiment, a plurality of first high electron mobilitytransistors 4 are coupled to the one second high electron mobilitytransistor 6, as illustrated in FIG. 6. Here, the first and the secondhigh electron mobility transistors 4, 6 are devices formed on anidentical substrate.

The structures of the first and the second high electron mobilitytransistors 4, 6 are substantially identical to the structures of thefirst and the second high electron mobility transistors according to theembodiment 1 which have been described by reference to FIGS. 2, 3. Aregion located between a region including the plurality of first highelectron mobility transistors 4 and a region including the second highelectron mobility transistor 6 is formed to have high resistance by ioninjection, for example.

Source terminal ST, drain terminal DT and gate terminal GT are electrodepads provided in a second insulating film 29 (refer to FIGS. 2, 3). Tothe above electrode pads, wirings 42 a, 42 b, 42 c provided on thesecond insulating film 29 are coupled. To the wirings 42 a, 42 b, 42 c,there are coupled the first and the second sources 51, S2, the first andthe second drains D1, D2, the first and the second gates G1, G2 and afield plate FP1 (hereafter referred to as the first source 51, S2, etc).The first source 51, S2, etc. and the wirings 42 a, 42 b, 42 c arecoupled by extraction electrodes 44 provided on the second insulatingfilm 29. Here, in FIG. 6, the first source 51, S2, etc. are drawn in astate the second insulating film 29 is seen through.

The structures of the first and the second high electron mobilitytransistors 4, 6 are substantially identical to the structures of thefirst and the second high electron mobility transistors explained in theembodiment 1, as described above. However, the first source 51 and thefirst drain D1 of each first high electron mobility transistor 4 areshared by each adjacent first high electron mobility transistor 4.

As illustrated in FIG. 6, in the transistor circuit 2 b according to thepresent embodiment, the plurality of first high electron mobilitytransistors 4 are coupled to the source terminal ST and the drainterminal DT. Therefore, high output power is obtainable.

FIG. 7 is a plan view of a deformation example 2c of the presentembodiment. In the deformation example 2c, a plurality of second highelectron mobility transistors 6 are disposed in the central portion ofthe transistor circuit 2 c. Further, in the deformation example 2c, aplurality of transistor regions 46 including a plurality of first highelectron mobility transistors 4 (not illustrated) are provided.

The plurality of second transistors 6 are respectively coupled to aplurality of first high electron mobility transistors 4 each included inany one of the plurality of transistor regions 46. Accordingly, theplurality of second high electron mobility transistors 6 disposed in thecentral portion share the limitation of the gate voltage rise of thefirst high electron mobility transistor 4 provided in the deformationexample 2c.

Because of the influence of the resistance and the parasitic capacitanceof the wirings 42 a, 42 b, 42 c, voltages to be applied to the firsthigh electron mobility transistors 4 differ device by device. By this,abnormal operation may easily occur in the transistor circuit having theplurality of first high electron mobility transistors 4.

Voltage dispersion applied to the first high electron mobilitytransistors 4 is apt to be large at both ends of the transistor circuit2 c. To cope therewith, according to the present embodiment, thedispersion of the applied voltage is mitigated by the disposition of theplurality of second high electron mobility transistors 6 in the centralportion, as illustrated in FIG. 7. By this, the abnormal operation ofthe first high electron mobility transistors 4 is suppressed.

Additionally, the dispersion of the applied voltage may be mitigatedsimply by the disposition of the plurality of second high electronmobility transistors 6 in a distributed manner.

Embodiment 3

FIG. 8 is a circuit diagram of a transistor circuit 2 d according to thepresent embodiment. As illustrated in FIG. 8, the transistor circuit 2 dresembles the transistor circuit 2 of the embodiment 1. Therefore, thedescription of portions common to the transistor circuit 2 of theembodiment 1 will be omitted.

As illustrated in FIG. 8, the transistor circuit 2 d includes a firsthigh electron mobility transistor 4 a and a second high electronmobility transistor 6 a.

(1) First High Electron Mobility Transistor

The first high electron mobility transistor 4 a includes a first gateG1, a first field plate FP1 a, and a second field plate FP2.

Similar to the first field plate FP1 in the embodiment 1, the firstfield plate FP1 a is a field plate provided between the first gate G1and a first drain D1. The first field plate FP1 a may be a field plateof which one portion extends between the first gate G1 and the firstdrain D1 (refer to “Gate and field plate structures” described later).

The second field plate FP2 is a field plate provided between the firstfield plate FP1 a and the first drain D1. The field plate FP2 may be afield plate of which one portion extends between the first field plateFP1 a and the first drain D1 (refer to “Gate and field plate structures”described later).

As illustrated in FIG. 8, the first high electron mobility transistor 4a includes a HEMT 32 corresponding to the first gate G1, a first FP-HEMT34 a corresponding to the first field plate FP1 a, and a second FP-HEMT48 corresponding to the second field plate FP2.

Similar to the embodiment 1, the HEMT 32 corresponding to the first gateG1 has a positive threshold (for example, 1 to 3 V). Also, the firstFP-HEMT 34 a has a negative threshold voltage (for example, in the orderof −7 to −8 V). The second FP-HEMT 48 has a negative threshold voltage(for example, in the order of −80 V) which is lower than the thresholdof the first FP-HEMT 34 a.

Also, similar to the embodiment 1, a source terminal ST is grounded, anda positive potential is supplied to a drain terminal DT. On the otherhand, the first field plate FP1 a is coupled to the first gate G1,differently from the first field plate FP1 in the embodiment 1. Also,the second field plate FP2 is coupled to the first gate G1.

When a low level potential (for example, 0 V) is applied to the firstgate G1, the HEMT 32 corresponding to the first gate G1 becomesnon-conductive. The potential of the first field plate FP1 a at thistime is a low level potential. Therefore, the potential at a first nodeN1 (node between the first gate G1 and the first field plate FP1 a)rises to a potential in which the threshold absolute value of the firstFP-HEMT 34 a (for example, 7 to 8 V) is added to the low level potential(for example, 0 V).

The threshold absolute value of the first FP-HEMT 34 a (for example, inthe order of 7 to 8 V) is lower than the gate withstand voltage of thefirst gate G1 (for example, in the order of 10 Vr), similar to theembodiment 1. Therefore, the first gate G1 is not broken by thepotential at the first node N1.

Similarly, when the low level potential is applied to the first gate G1,the potential at a second node N2 rises to a potential in which thethreshold absolute value of the second FP-HEMT 48 (for example, in theorder of 80 V) is added to the low level potential (for example, in theorder of 0 V). The second node N2 is a node between the first fieldplate FP1 a and the second field plate FP2.

The threshold absolute value of the second FP-HEMT 48 (for example, 80 Vor of that order) is lower than the gate withstand voltage of the firstFP-HEMT 34 a (for example, 100 V or of that order). Therefore, the firstFP is not broken by the potential at the second node N2.

The gate withstand voltage of the second field plate FP2 (for example,in the order of 1 kV) is higher than the gate withstand voltage of thefirst FP-HEMT 34 a (for example, in the order of 100 V). Therefore, thesecond FP-HEMT 48 may not be broken even if a potential higher than thegate withstand voltage of the first field plate FP1 a is applied to thedrain terminal DT.

Therefore, according to the present embodiment, the withstand voltage ofthe transistor circuit 2 d relative to a voltage between the sourceterminal ST and the drain terminal DT becomes higher than the withstandvoltage of the transistor circuit in the embodiments 1 and 2 includingno second field plate FP2. For example, the transistor circuit 2 d maynot be broken even if a noise voltage of the order of several hundredvolts is input to the drain terminal DT.

(2) Second High Electron Mobility Transistor

The second high electron mobility transistor 6 a includes a second gateG2 and a third field plate FP3. The second gate G2 and the third fieldplate FP3 are coupled to the source 51 of the first high electronmobility transistor 4 a.

The third field plate FP3 is a field plate provided between the secondgate G2 and the gate terminal GT. The third field plate FP3 may also bea field plate of which portion extends between the second gate G2 andthe gate terminal GT (refer to the “Gate and field plate structures”described later).

As illustrated in FIG. 8, the second high electron mobility transistor 6a includes a HEMT 50 corresponding to the second gate G2 and a thirdFP-HEMT 52 corresponding to the third field plate FP3.

Similar to the embodiment 1, the HEMT 50 corresponding to the secondgate G2 has a negative threshold voltage (for example, in the order of−7 to −8). The third FP-HEMT 52 has a negative threshold voltage (forexample, in the order of −80 V) lower than the threshold voltage of theHEMT 50 corresponding to the second gate G2.

In a state that a low level potential is applied to the gate terminalGT, the HEMT 50 corresponding to the second gate G2 and the thirdFP-HEMT 52 are conductive. When a potential applied to the gate terminalGT rises, the source-gate capacitance of the HEMT 32 corresponding tothe first gate G1 is charged. As a result, the source potential of theHEMT 50 corresponding to the second gate G2 rises.

When the gate drive potential (potential applied to the gate terminalGT) exceeds the threshold absolute value of the HEMT 50 corresponding tothe second gate G2, the source-gate voltage thereof becomes lower thanthe threshold. Therefore, the HEMT 50 corresponding to the second gateG2 becomes a non-conductive state. As a result, the potential at thefirst gate G1 is fixed approximately to the threshold absolute value ofthe HEMT 50 corresponding to the second gate G2.

When the gate drive potential further rises to exceed the thresholdabsolute value of the third FP-HEMT 52, the third FP-HEMT 52 becomes anon-conductive state. As a result, the potential at the third node N3between the second gate G2 and the third field plate FP3 is fixed to thethreshold absolute value of the third FP-HEMT 52, or to that degree.

The threshold absolute value of the HEMT 50 (for example, in the orderof 7 to 8 V) corresponding to the second gate G2 is lower than the gatewithstand voltage of the HEMT 32 (for example, in the order of 10 V)corresponding to the first gate G1, similar to the embodiment 1.Therefore, the first gate is not broken by the potential at the secondsource S2 (i.e. the potential at the first gate G1).

Also, the threshold absolute value of the third FP-HEMT 52 (for example,in the order of 80 V) is lower than the gate withstand voltage of theHEMT 50 (for example, in the order of 100 V) corresponding to the secondgate G2. Therefore, the second gate G2 is not broken by the potential atthe third node N3.

The withstand voltage of the third field plate (for example, in theorder of 1 kV) is higher than the withstand voltage of the second gateG2 (for example, in the order of 100 V). Therefore, the third FP-HEMT 52may not be broken even if a potential (for example, several hundredvolts) higher than the withstand voltage of the second gate G2 isapplied to the gate terminal GT.

Therefore, according to the present embodiment, the withstand voltage ofthe first gate G1 relative to the voltage between the source terminal STand the gate terminal GT becomes higher than the withstand voltage ofthe transistor circuit according to the embodiments 1 and 2 including nothird FP-HEMT 52. For example, the transistor circuit 2 d may not bebroken even if a noise voltage of the order of several hundred volts isinput to the gate terminal GT.

(3) Gate and Field Plate Structures

FIG. 9 illustrates an exemplary cross-sectional view of the first highelectron mobility transistor 4 a.

As illustrated in FIG. 9, the first high electron mobility transistor 4a includes a first compound semiconductor film (channel layer 12) and alaminated film 26. In the laminated film 26, a second compoundsemiconductor film (barrier layer 14) and a first insulating film 24 arelaminated.

The first high electron mobility transistor 4 a includes a firstelectrode 54 disposed between the first source 51 and the second drainD1. The first electrode 54 includes a first portion 56 embedded in afirst recess 28 b formed on the laminated film 26, and a plate-shapedsecond portion 58 extending on both the first portion 56 and the firstinsulating film 24. A third gate insulating layer 30 c is providedbetween the first electrode 54 and the laminated film 26. The secondportion 58 has a certain length (for example, 0.1 to several μm).

The first portion 56 includes a plate-shaped first embedded portion 60having a first length (for example, 0.1 to several μm) in the extendingdirection of the second portion 58. Also, the first portion 56 includesa plate-shaped second embedded portion 62 disposed between the firstembedded portion 60 and the bottom of the first recess 28 b with asecond length (for example, 0.1 μm or greater), which is smaller thanthe first length, in the above-mentioned extending direction. Asillustrated in FIG. 9, the above extending direction is a direction fromthe source S1 toward the drain D1 of the first high electron mobilitytransistor 4 a.

In the example illustrated in FIG. 9, the first recess 28 b reachesinside the barrier layer 14. However, the first recess 28 b may notreach inside the barrier layer 14. In other words, the first recess 28 bmay be stopped at the surface of the barrier layer 14 or inside thefirst insulating film 24. When the first recess 28 b is stopped insidethe first insulating film 24, the third gate insulating layer 30 c maybe omitted.

The second embedded portion 62 is the first gate G1. The first embeddedportion 60 is the first field plate FP1. The second portion 58 is thesecond field plate FP2. The first embedded portion 60, the secondembedded portion 62 and the second portion 58 are integrally formed andcoupled to each other.

As illustrated in FIG. 9, the first field plate FP1 (the first embeddedportion 60) expands to both sides of the first gate G1 (the secondembedded portion 62). One side of the above expanding portion (a portionof the first field plate FP1) extends between the first gate G1 (thesecond embedded portion 62) and the first drain D1, as illustrated inFIG. 9. The above portion functions as a field plate, so as to limit apotential at a boundary between with the first gate G1 to the thresholdabsolute value of the first field plate FP1 or to that degree.

Further, the second field plate FP2 (the second portion 58) expands toboth sides of the first field plate FP1 (the first embedded portion 60).One side of the above expansion (a portion of the second field plateFP2) extends between the first field plate FP1 (the first embeddedportion 60) and the first drain D1. One side of the above expansionfunctions as a field plate, and limits a potential at a boundary betweenwith the first field plate FP1 to the threshold absolute value of thesecond field plate FP2, or to that degree.

Namely, the first electrode 54 is an electrode in which the first gateG1, the first field plate FP1, and the second field plate FP2 arecombined.

FIG. 10 illustrates an exemplary cross-sectional view of the second highelectron mobility transistor 6 a.

As illustrated in FIG. 10, the second high electron mobility transistor6 a includes a first compound semiconductor film (channel layer 12) anda laminated film 26. In the laminated film 26, a second compoundsemiconductor film (a barrier layer 14) and a first insulating film 24are laminated.

The second high electron mobility transistor 6 a includes a secondelectrode 54 a disposed between the second source S2 and the seconddrain D2. The second electrode 54 a includes a plate-shaped firstportion 56 a embedded in a second recess 28 c formed on the laminatedfilm 26 with a certain length (for example, 0.1 to several μm). Also,the second electrode 54 a includes a plate-shaped second portion 58 aextending on both the first portion 56 a and the first insulating film24.

Between the second electrode 54 a and the laminated film 26, a fourthgate insulating layer 30 d is provided. In the example illustrated inFIG. 10, the second recess 28 c reaches the surface of the barrier layer14. However, the second recess 28 c may be stopped inside the firstinsulating film 24. When the second recess 28 c is stopped inside thefirst insulating film 24, the fourth gate insulating layer 30 d may beomitted.

The first portion 56 a is the second gate G2. The second portion 58 a isthe third field plate FP3. The first portion 56 a and the second portion58 a are integrally formed and coupled to each other.

A portion of the third field plate FP3 (the second portion 58 a) extendsbetween the second gate G2 (the first portion 56 a) and the second drainD2, as illustrated in FIG. 10. The above portion functions as a fieldplate, and limits a potential at a boundary between with the second gateG2 to the threshold absolute value of the third field plate FP3, or tothat degree.

In other words, the second electrode 54 a is an electrode in which thesecond gate G2 and the third field plate FP3 are combined.

(4) Manufacturing Method

FIGS. 11A through 15B are a process cross section illustrating anexemplary method for manufacturing a transistor circuit according to thepresent embodiment.

In the manufacturing processes illustrated in FIG. 11A through FIG. 15B,the method for manufacturing a transistor circuit further having afourth field plate FP4 between the first electrode 54 and the firstdrain D1 is described, as illustrated in FIG. 15B. The fourth fieldplate FP4 is coupled to the first source S1.

First, as illustrated in FIG. 11A, a Si substrate 64 is prepared. The Sisubstrate is a p-type (111) substrate, for example. By use of a metalorganic chemical vapor deposition etc., the following layers aresuccessively grown on the above Si substrate 64: an AlN buffer layer 66;a GaN layer (first compound semiconductor film) 68 with a thickness ofthe order of 20-40 nm, for example; an AlGaN layer (second compoundsemiconductor film) 70 with a thickness of the order of 10-30 nm, forexample; and a GaN layer 72 with a thickness of the order of 2-8 nm, forexample. Here, the above GaN layer 72 may be omitted.

Next, as illustrated in FIG. 11B, a photoresist film 76 having anaperture 74 corresponding to the first embedded portion 60 is formed onthe GaN layer 72. By use of the photoresist film 76 as a mask, a firstrecess region 78 reaching the AlGaN layer 70 is formed by dry etching. Afirst width of the first recess region 78 corresponding to the secondembedded portion 62 is in the order of 0.1 to several μm, for example.

After the photoresist film 76 is removed, SiN (not illustrated) forpreventing channeling is formed on the GaN layer 72 and the first recessregion 78. On the SiN film, a photoresist film (not illustrated) havingan aperture corresponding to a device isolation region 80 is formed. Byuse of the photoresist film as a mask, an Ar ion is injected at 100 kV,so that the device isolation region 80 is formed as illustrated in FIG.11C.

After the SiN for preventing channeling is removed, as illustrated inFIG. 12A, a SiN film (first insulating film) 82 with a thickness of200-400 nm is formed on the AlGaN layer 70 having the formed firstrecess region 78, and the GaN layer 72, by a plasma CVD (chemical vapordeposition) method.

Further, on the SiN layer 82, a photoresist film 86 having an aperture84 corresponding to the second embedded portion 62 of the first highelectron mobility transistor 4 a is formed. On the photoresist film 86,an aperture (not illustrated) corresponding to the first portion 56 a ofthe second high electron mobility transistor 6 a is also provided.

By dry etching the SiN film 82 using the photoresist film 86 as a mask,a second recess region 88, having a second width (for example, in theorder 0.2 to several μm) wider than the first width of the first recessregion 78, is formed on the SiN film 82. By this, the first recessregion 78 and the compound semiconductor layer on both sides of thefirst recess region are exposed.

After the photoresist film 86 is removed, an AlN film having a thicknessof, for example, 15-25 nm and a SiN film having a thickness of, forexample, 15-25 nm are successively deposited on the surfaces of the SiNfilm (the first insulating film) 82, having the formed second recessregion 88, and the exposed first recess region 78. By this, asillustrated in FIG. 12B, an insulating layer 90 is formed, which becomesa third gate insulating layer 30 c. The above AlN film and the SiN filmare formed by the ALD (atomic layer deposition) method and the plasmaCVD method, respectively.

By successively depositing TaN with a thickness of, for example, 40-60nm and an Al film with a thickness of, for example, 300-500 nm on theabove insulating layer 90, a conductive film 92 is formed, asillustrated in FIG. 12C.

On the conductive film 92, resist films 94 corresponding to the firstand the second electrodes 54, 54 a of the first and the second highelectron mobility transistors 4 a, 6 a are formed. Such a resist film 94is also formed at the formation position of the fourth field plate FP4.

By dry etching the conductive film 92 and the insulating layer 90 usingthe resist films 94 as masks, the first electrode 54, the secondelectrode 54 a (not illustrated), the fourth field plate FP4 and thethird through the fourth insulating layers 30 c-30 e are formed, asillustrated in FIG. 13A.

Thereafter, the resist films 94 are removed, and as illustrated in FIG.13B, a SiO₂ film 96 having a thickness of, for example, 200-400 nm isformed by the CVD method, using TEOS (tetraethyl orthosilicate) as a rawmaterial.

On the SiO₂ film 96, resist films 100 having 4 types of apertures 98respectively corresponding to the first and the second sources S1, S2and the first and the second drains D1, D2 (hereafter referred to as thefirst source S1, the first drain D1, etc.) are formed. Using the resistfilms 100 as masks, contact holes 102 reaching inside the AlGaN layer 70are formed, as illustrated in FIG. 13C.

Thereafter, the resist films 100 are removed, and a metal layer isformed by successively depositing a Ti film and an Al film by thesputtering method. On the metal layer, 4 types of resist films 104corresponding to the first source S1, the first drain D1, etc. areformed. Using the resist films 104 as masks, a metal layer 106 is etchedby dry etching, so that the first source S1, the first drain D1, etc.are formed, as illustrated in FIG. 14A.

After the resist films 104 are removed, a SiO₂ film 108 having athickness of the order of 1 μm is formed by the CVD method, using TEOSas a raw material. On the SiO₂ film 108, contact holes 110 correspondingto the extraction electrodes of the first source S1, the first drain D1,etc. are formed, as illustrated in FIG. 14B.

On the contact holes 110 and the SiO₂ film 108, for example, a Ti filmand an Al film having a thickness of the order 3 μm are depositedsuccessively. Thereafter, by shaping the Ti film and the Al film by thephotolithography method, extraction electrodes 44 are formed, asillustrated in FIG. 15A. At this time, the source terminal ST, the gateterminal GT, the drain terminal DT and the wirings 42 a-42 c (refer toFIG. 6) are also formed.

Thereafter, a SiO₂ film 112 and a SiN film 114 are successivelydeposited as illustrated in FIG. 15B, so that a cover film 116 isformed. Finally, on the cover film 116, apertures (not illustrated)corresponding to the source terminal ST, the gate terminal GT and thedrain terminal DT are formed.

According to the present manufacturing method, the second recess region88 is formed on the SiN film (the first insulating film) 82 which coversthe first recess region 78 (refer to FIG. 12A). The width of the secondrecess region 88 is greater than the width of the first recess region78. Therefore, it is easy to adjust a reticle position corresponding tothe second recess region 88, relative to the first recess region 78.Thus, according to the present manufacturing method, it is easilypossible to form the first and the second electrodes 54, 54 a.

According to the above-mentioned semiconductor devices 2-2 d, it ispossible to increase the withstand voltage of the high electron mobilitytransistor.

In the above-mentioned embodiments 1 through 3, the semiconductorheterojunction 10 is the GaN/AlGaN heterojunction. However, thesemiconductor heterojunction 10 may also be other semiconductorheterojunctions. For example, the semiconductor heterojunction 10 may bea GaAs/AlGaAs heterojunction.

All examples and conditional language recited herein are intended forpedagogical purposes to aid the reader in understanding the inventionand the concepts contributed by the inventor to furthering the art, andare to be construed as being without limitation to such specificallyrecited examples and conditions, nor does the organization of suchexamples in the specification relate to a showing of the superiority andinferiority of the invention. Although the embodiments of the presentinvention have been described in detail, it should be understood thatthe various changes, substitutions, and alterations could be made heretowithout departing from the spirit and scope of the invention.

What is claimed is:
 1. A semiconductor device comprising: a firstcompound semiconductor film; a laminated film in which a second compoundsemiconductor film and an insulating film are laminated and an electrodeincluding a first portion embedded in a recess formed on the laminatedfilm and a second portion extending on both the first portion and theinsulating film, wherein the first portion includes a first embeddedportion including a first length in an extending direction of the secondportion and a second embedded portion disposed between the firstembedded portion and a bottom of the recess with a second length smallerthan the first length.
 2. The semiconductor device according to claim 1,wherein the recess reaches inside the second compound semiconductorfilm.
 3. The semiconductor device according to claim 1, wherein therecess reaches a surface of the second compound semiconductor film or isstopped inside the first insulating film.
 4. The semiconductor deviceaccording to claim 1, wherein an insulating layer is provided betweenthe electrode and the laminated film.
 5. The semiconductor deviceaccording to claim 1, wherein the second portion expands to both sidesof the first portion, and the first embedded portion expands to bothsides of the second embedded portion.
 6. The semiconductor deviceaccording to claim 1, wherein the semiconductor device is a highelectron mobility transistor, the first compound semiconductor film is achannel layer of the high electron mobility transistor, the secondcompound semiconductor film is a barrier layer of the high electronmobility transistor, the electrode is an electrode in which a gate andtwo field plates are combined, and the extending direction is adirection from the source toward the drain of the high electron mobilitytransistor.